Timing Foundations

Why Static Timing Analysis

Functional verification asks "does the logic compute the right values?" Timing verification asks a different question: does every value arrive before the clock edge that consumes it? You could try to answer it dynamically — simulate with delays, watch waveforms — but timing depends on which paths the data actually exercises, and exercising all of them needs every input/state combination. The lab below lets you feel how fast 2ⁿ kills that plan.

Static timing analysis abandons vectors entirely. It reads the design as a graph: pins are nodes, timing arcs (through cells, along nets) are edges. It computes the worst-case arrival time at every node by propagating delays through the graph — once, input-independently — and compares each arrival against the time the consuming flop requires. Three properties make this the signoff standard:

• Complete — every structural path is covered, including ones no sane testbench would ever sensitize.
• Fast — graph traversal is roughly linear in design size; a full SoC times overnight, not over a career.
• Conservative — worst-case assumptions everywhere mean false alarms happen (a "violating" path that's never functionally exercised — Module 7 handles those), but a clean STA report means silicon timing is safe. Pessimism is the price; Modules 9's CRPR is the refund counter.

Delay, Slew & Transition

Digital diagrams draw vertical edges; silicon draws ramps. Two measurements characterize every transition:

• Delay — measured between the 50% points of input and output crossings (conventions vary slightly per library, but half-rail is standard).
• Slew / transition time — how long the edge itself takes, measured between threshold points (commonly 10–90% or 20–80% of VDD; the .lib states which).

The non-obvious part — the thing that makes slew a first-class citizen of STA rather than trivia — is that slew propagates. A slow edge at a gate's input means its transistors switch gradually, so the gate responds more slowly and produces a degraded output edge, which slows the next gate. Delay depends on input slew and output load; output slew also depends on both. That's why Module 2's library tables are two-dimensional, indexed by exactly those two quantities, and why STA must carry (arrival, slew) pairs through the whole graph, not just arrivals.

RC: the Physics of Late

Strip any digital delay to its skeleton and you find the same machine: a resistance charging a capacitance. The driving gate's transistors are the R (stronger gate = lower R); the wire and every input pin hanging on it are the C. The output voltage follows the exponential:

V(t) = VDD · (1 − e^(−t/τ)),   τ = R·C
t(50%) ≈ 0.69·τ      // the delay measurement
t(90%) ≈ 2.3·τ       // the slew tail — why slow edges drag on

From this single equation, read off the design levers you'll use forever:

• Upsize the driver → R halves → delay halves. (But the bigger gate presents more input capacitance to its driver — sizing is a chain negotiation, the heart of Module 12's ECOs.)
• Reduce the load → fewer fanouts, shorter wire → C drops.
• Split long wires with buffers → wire delay grows with the square of length (R and C both grow linearly); a repeater in the middle turns one quadratic into two small quadratics. This is why routed designs are full of buffers (RouteForge covers the insertion side).

The STA Worldview

Before the deep modules, calibrate on what STA fundamentally is and is not. The tool's world contains exactly: a netlist (cells + connectivity), libraries (Module 2), parasitics (Module 8), and your constraints (Modules 6–7). From those it computes arrivals, requireds, and slacks. It does not know what your logic means, which states are reachable, or what the chip is for.

Internalize the implication: STA is a constraint amplifier. Correct constraints → exhaustive verification for free. Wrong constraints → exhaustively verified nonsense, stamped "signoff clean". This is why senior engineers review SDC like contract lawyers (Module 6 trains you to be one) and why every timing course that skips constraints produces dangerous graduates.